1. Field of the Invention
The present invention relates generally to micro-electronic packaging, especially methods of manufacturing chip scale packages for high density integrated circuits with the aid of printing technology for printing solder and dielectric polymers.
2. Description of the Prior Art
The electronic package serves many purposes from protecting the integrated circuit (I.C.) to electrically connecting it to the outside world. Some of the functions that the micro-electronic package performs are: 1.) mechanically supporting the I.C.; 2.) protecting the I.C. from damage of environmental stresses including mechanical stress, thermal stress, stress induced by gain or loss of moisture, etc.; 3.) removing thermal energy created in the I.C.; 4.) connecting the I.C. to the outside world with the necessary inputs, outputs, grounds and power connections; 5.) shielding the surroundings from EMI created on the chip or created by the package leads; and 6.) minimizing overall size depending upon the application requirements.
A conventional method of packaging utilizes lead frames and strips having a die bonding center surface surrounded by leads. Curable adhesive is placed on the bonding surface of the lead frame and the integrated circuit chips pressed into the adhesive and subsequently cured to secure the chip to the frame. A similar process is also done on elongated printed circuit boards or ceramic substrates with conductors. Conventional processing further includes a wire bonder where tiny wires from pads on the chip are connected to the leads and the lead frame for electrical interconnects. Still further processing runs the lead frame to another machine called a mold machine which molds a plastic around and over successive chips to protect them. After the strip comes out of the mold machine, individual micro chips are trimmed out of the lead frame with electrical leads extending from the plastic shell. This process and an improvement thereof is discussed in U.S. Pat. No. 5,681,757.
The increase in the number of inputs and outputs and higher speed operations have driven the semiconductor packages to Array Bonding where the interconnect pads are spread out over the surface of the integrated circuit. The number of input-outputs and the high frequency operations of the main drivers of Array Bonding. In order to meet these requirements, integrated circuit packages are getting smaller, with interconnects covering the bottom surface of the package. Various types of packages exist, including Ball Grid Arrays, Micro Ball Grid Arrays, Flip-Chip, and Chip Scale Packages.
The prior art uses standard semiconductor and micro-electronic packaging technologies to reduce the size of the existing semiconductor package and create shorter interconnects. The prior art divides the semiconductor wafer into individual integrated circuits and then packages integrated circuits individually. Typically, the integrated circuits are placed in a package and sealed for protection. The best chip scale packages produced by prior art methods are 20% or more larger than the chip. As the devices get smaller and smaller, it would be advantageous to build the package directly onto the semiconductor wafer and then divide the wafer into individual semiconductors. The package would be no larger than the chip itself except in the thickness dimension. The prior art does not print the package directly onto integrated circuit chips or the semiconductor wafer. It would be highly desirable to provide a method based on printing technologies to print the package directly onto the semiconductor wafer. An object of the present invention is to provide such a packaging technology.